Many semiconductor processes for fabricating integrated circuit structures involve formation of field or isolation oxide, i.e., by Local Oxidation Of Silicon (LOCOS), along the semiconductor surface to provide electrical isolation between devices. Generally, the substrate surface is covered with a thin thermal oxide followed by a silicon nitride deposition. The nitride is then patterned to cover areas which are to become active regions, while other regions undergo an oxidation in order to form the field oxide. In addition, further steps may be taken to prevent turn-on of parasitic devices in the semiconductor crystal underlying the field oxide. By way of example, when NMOS devices are formed on a P-type substrate, ion implantation, e.g., with boron, is performed to increase the dopant level under the field oxide thereby, in combination with the thick field oxide, raising the threshold turn-on voltage of any parasitic device which extends under the field oxide. Generally, for MOS parasitics the threshold voltage is kept to a level which prevents fields associated with voltages in the overlying gate layer, source or drain conductors, or other interconnect from rendering the parasitic device conductive.
Numerous problems have been reported in cases where channel stop implants are used in combination with field oxides. See Wolf, Silicon Processing for the VLSI Era, Volume 21, Chapter 2 for a general discussion. Specifically, lattice dislocations generated during channel stop implantation are known to result in stacking faults during subsequent thermal processing such as the aforementioned field oxide growth. When these oxidation induced stacking faults (OISFs) extend into the active regions they can cause leakage currents which degrade device performance. In the past this has meant that certain performance specifications could only be met at the expense of others. Thus, in order to design an isolation structure with minimimally sufficient parasitic threshold voltages, it may be necessary to tolerate more leakage current than desired or accept less area efficiency. Several solutions have been identified to minimize such trade-offs. For example, field oxide growth under High Pressure Oxidation can limit dopant diffusion by reducing the oxide growth temperature while sustaining a high rate of oxidation; and a combined germanium-boron implant favorably reduces the born diffusion rate, thereby reducing the loss of boron by diffusion into the oxide and by lateral diffusion. It is also well known that with a chlorine implant the oxidation rate can be increased and the time required for oxide growth shortened. That is, by growing the field oxide faster there is less time for a highly mobile dopant species such as boron to diffuse into the oxide and, overall, a lower implant dose can be used to create the channel stop. Lower implant doses result in less lattice damage.
Notwithstanding the above-described process enhancements, development of stacking faults during the field isolation process continues to require significant trade-offs in order to achieve necessary field threshold voltages to prevent turn-on of parasitic devices. Absent such OISFs, parasitic threshold turn-on voltages could be further improved while also advancing to higher levels of mixed signal integration. It would, for example, become possible to further increase the density of integrated circuits containing power devices, low voltage CMOS logic and high voltage analog transistors.
The OISF problem may be best understood with reference to an example process sequence applicable to a high volume, highly cost sensitive manufacturing environment. The starting material is a wafer of lightly doped p-type monocrystalline silicon. After growth of a thin oxide layer on the wafer surface, active device regions are defined over the semiconductor surface with patterned silicon nitride. It is common to form the channel stop regions in alignment with the nitride pattern before growing the overlying field oxide. In the case of an n-channel field device, a p-type channel stop implant, e.g., boron, is used, while in the case of a p-channel field device, an n-type channel stop implant, e.g., phosphorous, is employed. In order to sustain a minimum 15 volt parasitic field threshold voltage a boron implant dose of at least 1E14/cm2would normally be required. A dose of this magnitude is known to impart lattice damage of the type which seeds OISFs during subsequent LOCOS. Due to the thickness of field oxide which typically must be grown under the cost constraints of volume manufacturing, LOCOS is commonly performed at a relatively high oxide growth rate, e.g., 1 micron thick in 3 hours of oxidation. Rapid growth normally occurs under relatively high thermal conditions with the undesirable diffusion of high mobility dopant species such as boron. OISF growth is known to occur under such rapid oxidation conditions.
There is now provided an improved process for isolating active regions of semiconductor devices with the combination of channel stop implantation and field oxide growth. The process minimizes or eliminates OISF's while permitting high-dose, e.g., 1E14/cm2 and higher, channel stop implants. The process is amenable to include techniques for reducing undesirable dopant diffusion, thereby allowing for a higher ratio of achievable parasitic threshold voltage to implant dose.
Generally, the process is a method for electrically isolating semiconductor devices in an integrated circuit structure with high field threshold, low defect level regions. The semiconductor structure includes a device layer predominantly comprising lattice silicon with a surface suitable for device formation. Multiple device regions are defined and field regions are defined for electrically isolating the device regions from one another. Dopant species are implanted to create a channel stop adjacent two of the device regions. The implant is of sufficient energy and concentration to impart within the device layer nucleation sites of the type known to result in stacking faults during oxide growth conditions. A thickness of thermally grown silicon dioxide is formed in the field regions by first thermally processing the integrated circuit structure to remove nucleation sites from the device layer and form a minor portion of the field oxide thickness; and subsequently forming a major portion of the oxide thickness under relatively fast growth conditions.